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PIC16F882-I Datasheet(PDF) 261 Page - Microchip Technology

Part # PIC16F882-I
Description  28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers
PDF  328 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F882-I Datasheet(HTML) 261 Page - Microchip Technology

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© 2009 Microchip Technology Inc.
DS41291F-page 259
PIC16F882/883/884/886/887
TABLE 17-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C
≤ TA ≤ +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
30
TMCLMCLR Pulse Width (low)
2
5
—
—
—
—
μs
μs
VDD = 5V, -40°C to +85°C
VDD = 5V
31
TWDT
Watchdog Timer Time-out
Period (No Prescaler)
10
10
16
16
29
31
ms
ms
VDD = 5V, -40°C to +85°C
VDD = 5V
32
TOST
Oscillation Start-up Timer
Period(1, 2)
—1024
—
TOSC (NOTE 3)
33*
TPWRT
Power-up Timer Period
40
65
140
ms
34*
TIOZ
I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
——
2.0
μs
35
VBOR
Brown-out Reset Voltage
2.0
—
2.2
V
BOR4V bit = 0 (NOTE 4)
3.6
4.0
4.4
V
BOR4V bit = 1, -40°C to +85°C
(NOTE 4)
3.6
4.0
4.5
V
BOR4V bit = 1, -40°C to +125°C
(NOTE 4)
36*
VHYST
Brown-out Reset Hysteresis
—
50
—
mV
37*
TBOR
Brown-out Reset Minimum
Detection Period
100
—
—
μsVDD ≤ VBOR
*
These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2:
By design.
3:
Period of the slower clock.
4:
To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1
μF and 0.01 μF values in parallel are recommended.



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