64GA106 datasheet(179/330 Pages) MICROCHIP

179 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 179

PIC24FJ256GA110 FAMILY

bit 1

SPITBF:

SPIx Transmit Buffer Full Status bit

= Transmit not yet started, SPIxTXB is full

= Transmit started, SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically

cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.

Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0

SPIRBF:

SPIx Receive Buffer Full Status bit

= Receive complete, SPIxRXB is full

= Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically

cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread

buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from

SPIxSR.

SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)

Note 1:

If SPIEN = 1, these functions must be assigned to available RPn pins (or to ASCK1 for the SCK1 output)

before use. See Section 10.4 “Peripheral Pin Select” for more information.

64GA106 Datasheet(PDF) 179 Page - Microchip Technology