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AS5134

Datasheet - Detailed Descr i pti on

7.9 Brushless DC Motor Commutation Mode

The BLDC signals will be used to control the electrical angle information – according to the amount of pole pairs and the actual mechanical angle

position. Refer Figure 13 for an example of n_pole_pairs:=2. For the programming, refer to Serial Synchronous Interface (SSI) on page 18.

Figure 13. Commutation Mode

7.10 Daisy Chain Mode

The angle information from the device and the setup for the device is handled over the digital interface. A special port (Dx) can be used to

implement a daisy chain mode. Depending on the configuration, it is possible to implement a two wire or a three wire mode. In the three wire

mode, each communication starts with the rising edge of the chip select signal. The Port Dx is used to transfer the chip select information from

one device to the next. Refer to Figure 14 and Figure 15. In the two wire interface mode, a timeout logic ensures that the digital interface will be

reset if there is no clock source available for a certain time. The synchronization between the internal free running analog clock oscillator and the

external used digital clock source for the digital interface is done in a way that the digital clock frequency can vary in a wide range.

Remark: Reset for the digital interface:

3 wire mode

 via chip select

2 wire mode

 via timeout

Table 8. Programming Options for the Commutation Signals U/V/W

uvw (11:9)

Function

0

0

0

BLDC Pole Pairs : 1

 electrical angle of 60º = mechanical angle: 60º

0

0

1

BLDC Pole Pairs : 2

 electrical angle of 60º = mechanical angle: 30º

0

1

0

BLDC Pole Pairs : 3

 electrical angle of 60º = mechanical angle: 20º

0

1

1

BLDC Pole Pairs : 4

 electrical angle of 60º = mechanical angle: 15º

1

0

0

BLDC Pole Pairs : 5

 electrical angle of 60º = mechanical angle: 12º

1

0

1

BLDC Pole Pairs : 6

 electrical angle of 60º = mechanical angle: 10º

11

1

off

 LO pad U, V, W, PWM

Port

Symbol

Function

Chip Select

CS

Indicates the start of a new access cycle to the device

CS = LO

 reset of the digital interface.

DCLK

DCLK

Clock source for the communication over the digital interface. The maximum and

minimum frequency depends on the mode.

120

180

240

300

120

180

180

120

240

270

210

150

60

0

0

60

60

90

30

0

angle electrical

angle mechanical

U

V

W

pole pair : 2