Block Diagram

writing of up to 64-bytes simultaneously. During a write cy-

cle, the addresses and 1 to 64-bytes of data are internally

latched, freeing the address and data bus for other opera-

tions. Following the initiation of a write cycle, the device

will automatically write the latched data using an internal

control timer. The end of a write cycle can be detected by

DATA Polling of I/O7. Once the end of a write cycle has

been detected, a new access for a read or write can begin.

Atmel’s AT28HC64B has additional features to ensure

high quality and manufacturability. The device utilizes in-

ternal error correction for extended endurance and im-

proved data retention. An optional software data protec-

tion mechanism is available to guard against inadvertent

writes. The device also includes an extra 64-bytes of

EEPROM for device identification or tracking.

Description (Continued)

Temperature Under Bias................. -55°C to +125°C

Storage Temperature...................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

Voltage on OE and A9

with Respect to Ground ................... -0.6V to +13.5V

*NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Absolute Maximum Ratings*

2-268

AT28HC64B