®

VFC100

9

R

IN

Clocked

Logic

Output

One-Shot

54

14

10

7

6

Clock

15

1

+V

CC

11

12

9

8

13

5V

Reference

16

0.1µF

+15VDC

0.1µF

–V

CC

f

OUT

±3.75mV

Offset Trim

+V

L

500

Ω

C

INT

2M

Ω

R

2

R

1

V

IN

±1% Gain Trim

20k

Ω

R

3

500

Ω

R

4

R

5

350k

Ω

–15VDC

0.1µF

+15VDC

–V

CC

FIGURE 9. Circuit Diagram for Fine Offset and Gain Trim.

0.03

0.02

0.01

0

3

2

1

0

0

500k

1M

f

– Full Scale Frequency (Hz)

FS

Gain Error

Nonlinearity

FIGURE 10. Typical Nonlinearity and Gain Error vs Full

Scale Frequency.

V

(V)

IN

0.015

0.01

0.005

0

–0.005

0

2468

10

at higher operating frequency. The VFC100’s gain drift

remains excellent at higher operating frequency, typically

Drift of the external clock frequency directly affects the

output frequency, but by using a common clock for the VFC

and counting circuitry, this drift can be cancelled (see

“Counting the Output”).

POWER SUPPLIES AND GROUNDING

Separate analog and digital grounds are provided on the

VFC100 and it is important to separate these grounds to

attain greatest accuracy. Logic sink current flowing in the

current were allowed to flow in analog ground, errors could

be created. Although analog and digital grounds may even-

tually be connected together at a common point in the

circuitry, separate circuit connections to this common point

can reduce the error voltages created by varying currents

flowing through the ground return impedance. The +5V

The power supplies should be well bypassed using capaci-

tors with low impedance at high frequency. A value of 0.1

µF

is adequate for most circuit layouts.

The VFC100 is specified for a nominal supply voltage of

±15V. Supply voltages ranging from ±7.5V to ±18V may be

used. Either supply can be up to 28V as long as the total of

both does not exceed 36V. Steps must be taken, however, to

assure that the integrator output does not exceed its linear

range. Although the integrator output is capable of 12V

output swing with 15V power supplies, with 7.5V supplies,

output swing will be limited to approximately 4.5V. In this

case, the comparator input cannot be offset by directly

connecting to the 5V reference output pin. The comparator

input must be connected to a lower voltage point (approxi-

mately 2V). This allows the integrator output to operate

around a lower voltage point, assuring linear operation. This

threshold voltage does not affect the accuracy or drift of the

VFC as long as it is not noisy. It should not be made too