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C8051F54X Datasheet(PDF) 1 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 275 page  Mixed Signal ISP Flash MCU Family C8051F54x Rev. 1.1 4/11 Copyright © 2011 by Silicon Laboratories C8051F540/1/2/3/4/5/6/7 Analog Peripherals - 12-Bit ADC • Up to 200 ksps • Up to 25 external single-ended inputs • VREF from on-chip VREF, external pin or VDD • Internal or external start of conversion source • Built-in temperature sensor - Two Comparators • Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current On-Chip Debug - On-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - Provides breakpoints, single stepping, inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - Low cost, complete development kit Supply Voltage 1.8 to 5.25 V - Typical operating current: 19 mA at 50 MHz; Typical stop mode current: 1 µA High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 50 MIPS throughput with 50 MHz clock - Expanded interrupt handler Memory - 1280 bytes internal data RAM (256 + 1024 XRAM) - 16 or 8 kB Flash; In-system programmable in 512-byte Sectors Digital Peripherals - 25 or 18 Port I/O; All 5 V tolerant - LIN 2.1 Controller (Master and Slave capable); no crystal required - Hardware enhanced UART, SMBus™, and enhanced SPI™ serial ports - Four general purpose 16-bit counter/timers - 16-Bit programmable counter array (PCA) with six capture/compare modules and enhanced PWM functionality Clock Sources - Internal 24 MHz with ±0.5% accuracy master LIN operation - External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) - Can switch between clock sources on-the-fly; useful in power saving modes Packages - 32-Pin QFP/QFN (C8051F540/1/4/5) - 24-Pin QFN (C8051F542/3/6/7) Automotive Qualified - Temperature Range: –40 to +125 °C - Compliant to AEC-Q100 ANALOG PERIPHERALS 16 kB ISP FLASH 1 kB XRAM POR DEBUG CIRCUITRY FLEXIBLE INTERRUPTS 8051 CPU (50 MIPS) DIGITAL I/O 24 MHz PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE WDT 2x Clock Multiplier UART 0 SMBus SPI PCA Timers 0-3 Crossbar LIN Ports 0-3 A M U X 12-bit 200 ksps ADC TEMP SENSOR Voltage Comparators 0-1 VREG VREF |
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