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C8051F124-GQR Datasheet(PDF) 92 Page - Silicon Laboratories |
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C8051F124-GQR Datasheet(HTML) 92 Page - Silicon Laboratories |
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92 / 350 page  C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 92 Rev. 1.4 7.2. ADC2 Modes of Operation ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock) is a divided version of the system clock, determined by the AD2SC bits in the ADC2CF register. The maximum ADC2 conversion clock is 6 MHz. 7.2.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC2 Start of Conversion Mode bits (AD2CM2-0) in ADC2CN. Conversions may be initiated by: 1. Writing a ‘1’ to the AD2BUSY bit of ADC2CN; 2. A Timer 3 overflow (i.e. timed continuous conversions); 3. A rising edge detected on the external ADC convert start signal, CNVSTR2; 4. A Timer 2 overflow (i.e. timed continuous conversions); 5. Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC2 and ADC0 with a single software command). During conversion, the AD2BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The falling edge of AD2BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC2CN. Con- verted data is available in the ADC2 data word, ADC2. When a conversion is initiated by writing a ‘1’ to AD2BUSY, it is recommended to poll AD2INT to determine when the conversion is complete. The recommended procedure is: Step 1. Write a ‘0’ to AD2INT; Step 2. Write a ‘1’ to AD2BUSY; Step 3. Poll AD2INT for ‘1’; Step 4. Process ADC2 data. When CNVSTR2 is used as a conversion start source, it must be enabled in the crossbar, and the corre- sponding pin must be set to open-drain, high-impedance mode (see Section “18. Port Input/Output” on page 235 for more details on Port I/O configuration). 7.2.2. Tracking Modes The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2 input is continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1, ADC2 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track- ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 signal is used to ini- tiate conversions in low-power tracking mode, ADC2 tracks only when CNVSTR2 is low; conversion begins on the rising edge of CNVSTR2 (see Figure 7.2). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power Track-and-Hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time requirements described in Section “7.2.3. Settling Time Requirements” on page 94 . |
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