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C8051F124-GQR Datasheet(PDF) 39 Page - Silicon Laboratories |
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C8051F124-GQR Datasheet(HTML) 39 Page - Silicon Laboratories |
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39 / 350 page  C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 39 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3 and C8051F130/1/2/3) –40 to +85 °C, 100 MHz System Clock unless otherwise specified. Parameter Conditions Min Typ Max Units Analog Supply Voltage1 SYSCLK = 0 to 50 MHz SYSCLK > 50 MHz 2.7 3.0 3.0 3.3 3.6 3.6 V V Analog Supply Current Internal REF, ADCs, DACs, Com- parators all active —1.7 — mA Analog Supply Current with analog sub-systems inactive Internal REF, ADCs, DACs, Com- parators all disabled, oscillator disabled —0.2 — µA Analog-to-Digital Supply Delta (|VDD –AV+|) —— 0.5 V Digital Supply Voltage SYSCLK = 0 to 50 MHz SYSCLK > 50 MHz 2.7 3.0 3.0 3.3 3.6 3.6 V V Digital Supply Current with CPU active VDD = 3.0 V, Clock = 100 MHz VDD = 3.0 V, Clock = 50 MHz VDD = 3.0 V, Clock = 1 MHz VDD = 3.0 V, Clock = 32 kHz —65 35 1 33 —mA mA mA µA Digital Supply Current with CPU inactive (not accessing Flash) VDD = 3.0 V, Clock = 100 MHz VDD = 3.0 V, Clock = 50 MHz VDD = 3.0 V, Clock = 1 MHz VDD = 3.0 V, Clock = 32 kHz —40 20 0.4 15 —mA mA mA µA Digital Supply Current (shut- down) Oscillator not running —0.4 — µA Digital Supply RAM Data Retention Voltage —1.5 — V SYSCLK (System Clock)2,3 VDD, AV+ = 2.7 to 3.6 V VDD, AV+ = 3.0 to 3.6 V 0 0 —50 100 MHz MHz Specified Operating Temper- ature Range –40 — +85 °C Notes: 1. Analog Supply AV+ must be greater than 1 V for VDD monitor to operate. 2. SYSCLK is the internal device clock. For operational speeds in excess of 30 MHz, SYSCLK must be derived from the Phase-Locked Loop (PLL). 3. SYSCLK must be at least 32 kHz to enable debugging. |
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