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C8051F124-GQR Datasheet(PDF) 41 Page - Silicon Laboratories |
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C8051F124-GQR Datasheet(HTML) 41 Page - Silicon Laboratories |
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41 / 350 page  C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 41 4. Pinout and Package Definitions Table 4.1. Pin Definitions Name Pin Numbers Type Description ‘F120 ‘F122 ‘F124 ‘F126 ‘F121 ‘F123 ‘F125 ‘F127 ‘F130 ‘F132 ‘F131 ‘F133 VDD 37, 64, 90 24, 41, 57 37, 64, 90 24, 41, 57 Digital Supply Voltage. Must be tied to +2.7 to +3.6 V. DGND 38, 63, 89 25, 40, 56 38, 63, 89 25, 40, 56 Digital Ground. Must be tied to Ground. AV+ 11, 14 6 11, 14 6 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. AGND 10, 13 5 10, 13 5 Analog Ground. Must be tied to Ground. TMS 1 58 1 58 D In JTAG Test Mode Select with internal pullup. TCK 2 59 2 59 D In JTAG Test Clock with internal pullup. TDI 3 60 3 60 D In JTAG Test Data Input with internal pullup. TDI is latched on the rising edge of TCK. TDO 4 61 4 61 D Out JTAG Test Data Output with internal pullup. Data is shifted out on TDO on the falling edge of TCK. TDO output is a tri-state driver. RST 5 62 5 62 D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven low when VDD is < VRST and MONEN is high. An external source can initiate a system reset by driving this pin low. XTAL1 26 17 26 17 A In Crystal Input. This pin is the return for the inter- nal oscillator circuit for a crystal or ceramic reso- nator. For a precision internal clock, connect a crystal or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external CMOS clock, this becomes the system clock. XTAL2 27 18 27 18 A Out Crystal Output. This pin is the excitation driver for a crystal or ceramic resonator. MONEN 28192819 D In VDD Monitor Enable. When tied high, this pin enables the internal VDD monitor, which forces a system reset when VDD is < VRST. When tied low, the internal VDD monitor is disabled. This pin must be tied high or low. |
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