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IO20PDB0V0 Datasheet(PDF) 176 Page - Microsemi Corporation |
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IO20PDB0V0 Datasheet(HTML) 176 Page - Microsemi Corporation |
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176 / 197 page ![]() Pin Descriptions 5- 62 R e v i sio n 1 2 M21 VPP VPP M22 IO32NDB1V0 IO41NDB1V0 N1 GND GND N2 NC IO70PDB5V0 N3 NC IO70NDB5V0 N4 VCCRCOSC VCCRCOSC N5 VCCFPGAIOB5 VCCFPGAIOB5 N6 NC IO68NDB5V0 N7 VCCFPGAIOB5 VCCFPGAIOB5 N8 GND GND N9 VCC VCC N10 GND GND N11 VCC VCC N12 GND GND N13 VCC VCC N14 GND GND N15 VCC VCC N16 NC GND N17 NC NC N18 VCCFPGAIOB1 VCCFPGAIOB1 N19 VCCENVM VCCENVM N20 GNDENVM GNDENVM N21 NC NC N22 GND GND P1 NC IO69NDB5V0 P2 NC IO69PDB5V0 P3 GNDRCOSC GNDRCOSC P4 GND GND P5 NC NC P6 NC NC P7 GND GND P8 VCC VCC P9 GND GND P10 VCC VCC Pin Number FG484 A2F200 Function A2F500 Function Notes: 1. Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 2. *: Indicates that the signal assigned to the pins as a CLKBUF/CLKBUF_LVPECL/CLKBUF_LVDS goes through a glitchless mux. In order for the glitchless mux to operate correctly, the signal must be a free-running clock signal. Refer to the ’Glitchless MUX’ section in the SmartFusion Microcontroller Subsystem User’s Guide for more details. |
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