IO10PDB0V0 datasheet(120/197 Pages) MICROSEMI

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Pin Descriptions

5- 6

R ev isio n 1 2

Global I/O Naming Conventions

Gmn (Gxxx) refers to Global I/Os. These Global I/Os are used to connect the input to global networks.

Global networks have high fanout and low skew. The naming convention for Global I/Os is as follows:

G = Global

m = Global pin location associated with each CCC on the device:

– A (northwest corner)

– B (northeast corner)

– C (east middle)

– D (southeast corner)

– E (southwest corner)

– F (west middle)

n = Global input MUX and pin number of the associated Global location m—A0, A1, A2, B0, B1, B2,

C0, C1, or C2.

Global (GL) I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct

access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since

they have identical capabilities.

Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global

I/O connectivity in the clocking resources chapter of the SmartFusion FPGA Fabric User’s Guide and the

clock conditioning circuitry chapter of the SmartFusion Microcontroller Subsystem User’s Guide.

All inputs other than GC/GF are direct inputs into the quadrant clocks. The inputs to the global network

are multiplexed, and only one input can be used as a global input. For example, if GAA0 is used as a

quadrant global input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All

inputs other than GC/GF are direct inputs into the chip-level globals, and the rest are connected to the

quadrant globals. For more details, refer to the Global Input Selections section of the SmartFusion Fabric

User Guide.

User Pins

Name

Type

Polarity/B

us Size

Description

GPIO_x

In/out

Microcontroller Subsystem (MSS) General Purpose I/O (GPIO). The MSS GPIO pin

functions as an input, output, tristate, or bidirectional buffer with configurable interrupt

generation and Schmitt trigger support. Input and output signal levels are compatible

with the I/O standard selected.

Unused GPIO pins are tristated and do not include pull-up or pull-down resistors.

During power-up, the used GPIO pins are tristated with no pull-up or pull-down

resistors until Sys boot configures them.

Some of these pins are also multiplexed with integrated peripherals in the MSS (SPI,

I2C, and UART). These pins are located in Bank-2 (GPIO_16 to GPIO_31) for A2F060,

A2F200, and A2F500 devices.

GPIOs can be routed to dedicated I/O buffers (MSSIOBUF) or in some cases to the

FPGA fabric interface through an IOMUX. This allows GPIO pins to be multiplexed as

either I/Os for the FPGA fabric, the ARM® Cortex-M3 or for given integrated MSS

peripherals. The MSS peripherals are not multiplexed with each other; they are

multiplexed only with the GPIO block. For more information, see the General Purpose

I/O Block (GPIO) section in the SmartFusion Microcontroller Subsystem User’s Guide.

In/out

FPGA user I/O

IO10PDB0V0 Datasheet(PDF) 120 Page - Microsemi Corporation

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