LM12454, LM12458, LM12H458

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SNAS079A – MAY 2004 – REVISED FEBRUARY 2006

Digital Timing Characteristics

(1) (2) (3)

Symbol (See

Figure 8

Parameter

Conditions

Units

Figure 9

Figure 11)

1, 3

CS or Address Valid to ALE Low Set-Up Time

40

ns (min)

2, 4

CS or Address Valid to ALE Low Hold Time

20

ns (min)

5

ALE Pulse Width

45

ns (min)

6

RD High to Next ALE High

35

ns (min)

7

ALE Low to RD Low

20

ns (min)

8

RD Pulse Width

100

ns (min)

9

RD High to Next RD or WR Low

100

ns (min)

10

ALE Low to WR Low

20

ns (min)

11

WR Pulse Width

60

ns (min)

12

WR High to Next ALE High

75

ns (min)

13

WR High to Next RD or WR Low

140

ns (min)

14

Data Valid to WR High Set-Up Time

40

ns (min)

15

Data Valid to WR High Hold Time

30

ns (min)

10

ns (min)

16

RD Low to Data Bus Out of TRI-STATE

40

70

ns (max)

10

ns (min)

17

RD High to TRI-STATE

30

110

ns (max)

10

ns (min)

18

RD Low to Data Valid (Access Time)

30

80

ns (max)

20

Address Valid or CS Low to RD Low

20

ns (min)

21

Address Valid or CS Low to WR Low

20

ns (min)

19

Address Invalid from RD or WR High

10

ns (min)

10

ns (min)

22

INT High from RD Low

30

60

ns (max)

10

ns (min)

23

DMARQ Low from RD Low

30

60

ns (max)

(1)

Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above

accurate conversions.

(2)

assure conversion/comparison accuracy.

(3)

(4)

(5)

Limits are to AOQL (Average Output Quality Level).

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