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AT42QT1110-AU Datasheet(PDF) 30 Page - ATMEL Corporation |
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AT42QT1110-AU Datasheet(HTML) 30 Page - ATMEL Corporation |
30 / 50 page ![]() 30 AT42QT1110-MU / AT42QT1110-AU [DATASHEET] 9520J–AT42–05/2013 SYNC: selects the trigger type when SYNC Pin is selected as the trigger to start key acquisition. 0 = Level Acquisition starts when a 0 is read at the SYNC pin. If the pin is held low, the QT1110 operates in Free run mode (that is, it will not sleep in between acquisitions, but start again immediately). 1 = Edge Acquisition starts when a rising edge is detected at the SYNC pin. When acquisition and post-processing are completed, the device sleeps until another rising edge is detected at the SYNC pin. REPEAT_TIME: selects the “repeat” time when “Timed” is selected as the trigger to start key acquisition. The number entered is a multiple of 16 ms. If 0 is entered, the device will operate in a continuous free run mode; that is, the QT1110 will not sleep after its cycle is completed but will begin the next key acquisition cycle immediately. Default KEY_AC value: 1 (timed) Default MODE value: 0 (7-key mode) Default SIGNAL value: 1 (parallel) Default SYNC value: 1 (edge) Default REPEAT_TIME value: 2 (32 ms cycle) 7.5 Address 1: Guard Key/Comms Options GUARD_KEY: specifies the key (0 to 10) to be used as a guard channel (see Section 2.3 on page 7) . GD_EN: enables the use of a guard key; 0 = disable, 1 = enable. SPI_EN: enables the Quick SPI interface; 0 = disable, 1 = enable. See Section 4.1.6 on page 16 for details of the Quick SPI Mode report. To exit this mode (and clear the SPI_EN bit), the command 0x36 should be sent. To save the settings to EEPROM and make Quick SPI mode active on startup, send the Store to EEPROM command (0x0A). Any other data sent is ignored in Quick SPI mode. CHG: the CHANGE pin mode (see Section 4.5 on page 18): 0 = Data mode. In this mode the CHANGE pin is asserted to indicate unread data. 1 = Touch mode. In this mode the CHANGE pin is asserted when a key is being touched or is in detect. CRC: enables or disables CRC; 0 = disable, 1 = enable. When this option is enabled, each data exchange must have a CRC byte appended. When report or setup data is being returned by the QT1110, a 1-byte checksum is returned. The host should confirm that this checksum is correct and, if not, should request the report again. Where data is being sent by the host, a 1-byte CRC should be sent. The QT1110 returns the expected CRC byte in the same transaction the CRC byte is sent. In this way, the host can immediately determine whether the setup data bytes were received correctly. Default GUARD_KEY value: 0 (Key 0) Default GD_EN value: 0 (disabled) Default CHG value: 0 (data mode) Default CRC value: 0 (disabled) Table 7-3. Guard Key/Comms Options Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 GUARD_KEY GD_EN SPI_EN CHG CRC |
Similar Part No. - AT42QT1110-AU_14 |
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Similar Description - AT42QT1110-AU_14 |
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