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AT42QT1110-AU Datasheet(PDF) 39 Page - ATMEL Corporation |
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AT42QT1110-AU Datasheet(HTML) 39 Page - ATMEL Corporation |
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39 / 50 page  39 AT42QT1110-MU / AT42QT1110-AU [DATASHEET] 9520J–AT42–05/2013 8.4 Timing Specifications 8.5 SPI Bus Specifications 8.5.1 General Specifications 8.5.2 Full SPI Mode Parameter Description Min Typ Max Units Notes TBS Burst duration – 5 – ms 4.7 nF Cs Fc Burst center frequency – 53 – kHz Fm Burst modulation, percentage – 18 – % TPW Pulse width – 6000 – ns Parameter Specification Address space 8-bit Maximum clock rate 1.5 MHz Minimum low clock period 333 ns Minimum high clock period 333 ns Clock idle High Setup on Leading (falling) edge Clock out on Trailing (rising) edge SPI Enable delay (SS low to SCK low) 1 µs minimum Parameter Specification Minimum time between bytes 150 µs Minimum time between communications Generally 150 µs; longer delays required to implement some commands, as follows: Send Setups: 150 µs after all setup bytes are returned Calibrate All: 150 µs Calibrate Key: 150 µs Reset: 160 ms Sleep: 150 µs after a low signal is applied to SS or CHANGE to wake the device Store to EEPROM: 200 ms Restore from EEPROM: 150 ms Erase EEPROM: 50 ms Recover EEPROM: 50 ms |
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