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ICS9148-26 Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS9148-26 Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 17 page ![]() 2 ICS9148-26 Pin Descriptions Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. PIN NUMBER PIN NAME TYPE DESCRIPTION 1 VDD1 PWR Ref (0:2), XTAL power supply, nominal 3.3V 2REF0 OUT 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads 3,9,16,22, 33,39,45 GND PWR Ground 4X1 IN Crystal input, has internal load cap (36pF) and feedback resistor from X2 5X2 OUT Crystal output, nominally 14.318MHz. Has internal load cap (36pF) 6,14 VDD2 PWR Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V 7 PCICLK_F OUT Free running PCI clock MODE 1, 2 IN Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 8 PCICLK0 OUT PCI clock output. 10, 11, 12, 13 PCICLK(1:4) OUT PCI clock outputs. 15 BUFFER IN IN Input to Fanout Buffers for SDRAM outputs. 18 PCI_STOP# 1 IN Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode, MODE=0) 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38,40,41 SDRAM (0:13) OUT (Pins 17, 18 SDRAM output only if MODE=High) SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). 19,30,36 VDD3 PWR Supply for SDRAM (0:13) and CPU PLL Core, nominal 3.3V. 23 SDATA IN Data input for I 2 C serial input, 5V tolerant input 24 SCLK IN Clock input of I 2 C input, 5V tolerant input 25 24MHz OUT 24MHz output clock FS1 1, 2 IN Frequency select pin. Latched Input. 26 48MHz OUT 48MHz output clock FS0 1, 2 IN Frequency select pin. Latched Input 27 VDD4 PWR Power for 24 & 48MHz output buffers and fixed PLL core. 43, 44 CPUCLK(0:1) OUT CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low 42 VDDL2 PWR Supply for CPU (0:1), either 2.5V or 3.3V nominal 46 REF1 OUT 14.318 MHz reference clock. FS2 1, 2 IN Frequency select pin. Latched Input 17 CPU_STOP# 1 IN Halts CPUCLK (0:1) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) 47 IOAPIC OUT IOAPIC clock output. 14.318 MHz Powered by VDDL1. 48 VDDL1 PWR Supply for IOAPIC, either 2.5 or 3.3V nominal |
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