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ADG799G Datasheet(PDF) 17 Page - Analog Devices |
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ADG799G Datasheet(HTML) 17 Page - Analog Devices |
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17 / 24 page  ADG799A/ADG799G Rev. 0 | Page 17 of 24 THEORY OF OPERATION The ADG799A/ADG799G are monolithic CMOS device comprising three 2 × 2 crosspoint switches controllable via a standard I2C serial interface. The CMOS process provides ultralow power dissipation, yet offers high switching speed and low on resistance. The on resistance profile is very flat over the full analog input range, and wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range, make the ADG799A/ADG799G an ideal switching solution for a wide range of TV applications. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The integrated serial I2C interface controls the operation of the crosspoint switches (ADG799A/ADG799G) and general- purpose logic pins (ADG799G only). The ADG799A/ADG799G have many attractive features, such as the ability to individually control each switch, the option of reading back the status of any switch. The ADG799G has two general- purpose logic output pins controllable through the I2C interface. The following sections describe these features in more detail. I2C SERIAL INTERFACE The ADG799A/ADG799G are controlled via an I2C-compatible serial bus interface (refer to the I2C-Bus Specification available from Philips Semiconductor) that allows the part to operate as a slave device (no clock is generated by the ADG799A/ADG799G). The communication protocol between the I2C master and the device operates as follows: 1. The master initiates data transfer by establishing a start condition (defined as a high-to-low transition on the SDA line while SCL is high). This indicates that an address/data stream follows. All slave devices connected to the bus respond to the start condition and shift in the next eight bits, consisting of a seven bit address (MSB first) plus an R/W bit. This bit determines the direction of the data flow during the communication between the master and the addressed slave device. 2. The slave device whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is known as the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. 3. Data transmits over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of the clock signal, SCL, and remain stable during the high period of SCL. Otherwise, a low-to-high transition when the clock signal is high can be interpreted as a stop event that ends the communication between the master and the addressed slave device. 4. After transferring all data bytes, the master establishes a stop condition, defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. I2C ADDRESS The ADG799A/ADG799G each have a seven-bit I2C address. The four most significant bits are internally hardwired while the last three bits (A0, A1, and A2) are user-adjustable. This allows the user to connect up to eight ADG799A/ADG799Gs to the same bus. The I2C bit map shows the configuration of the seven-bit address. Seven-Bit I2C Address Bit Configuration MSB LSB 1 0 1 0 A2 A1 A0 WRITE OPERATION When writing to the ADG799A/ADG799G, the user must begin with an address byte and R/W bit. Next, the switch acknowledges that it is prepared to receive data by pulling SDA low. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCL. Figure 31 illustrates the entire write sequence for the ADG799A/ADG799G. The first data byte (AX7 to AX0) controls the status of the crosspoint switches and the GPO pins, while the LDSW and RESETB bits from the second byte controls the operation mode of the device. Table 6 shows a list of all commands supported by the ADG799A/ADG799G with the corresponding byte that needs to be loaded during a write operation. To achieve the desired configuration, one or more commands can be loaded into the device. Any combination of the commands listed in Table 6 can be used with the following restrictions: • The commands referring to more than one switch overwrite any previous command. • When a sequence of successive commands affect the same element (that is, the switch or GPO pin), only the last command is executed. |
Similar Part No. - ADG799G_15 |
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Similar Description - ADG799G_15 |
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