15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/

LVTTL ZERO DELAY CLOCK BUFFER

86004 DATA SHEET

4

REVISION B 7/10/15

DD

= V

DDA

= V

DDO

DD

= V

DDA

= V

DDO

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

IH

Input High Voltage

V

DD

= 3.3V

2

V

DD

+ 0.3

V

V

DD

= 2.5V

1.7

V

DD

+ 0.3

V

V

IL

Input Low Voltage

V

DD

= 3.3V

-0.3

0.8

V

V

DD

= 2.5V

-0.3

0.7

V

I

IH

Input High Current

CLK, MR,

FB_IN, F_SEL

V

DD

= V

IN

= 3.465V

150

µA

PLL_SEL

V

DD

= V

IN

= 3.465V

5

µA

I

IL

Input Low Current

CLK, MR,

FB_IN, F_SEL

V

DD

= 3.465V, V

IN

= 0V

-5

µA

PLL_SEL

V

DD

= 3.465V, V

IN

= 0V

-150

µA

V

OH

Output High Voltage; NOTE 1

V

DDO

= 3.465V

2.6

V

V

DDO

= 2.625V

1.8

V

V

OL

Output Low Voltage; NOTE 1

V

DDO

= 3.465V or 2.625V

0.5

V

NOTE 1: Outputs terminated with 50

Ω to V

DDO

/2. See Parameter Measurement Information Section,

Output Load Test Circuit diagrams.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Output Frequency

F_SEL = 0

31.25

62.5

MHz

F_SEL = 1

15.625

31.25

MHz

tp

LH

Propagation Delay, Low-to-High; NOTE 1

PLL_SEL = 0V,

Bypass Mode

4.1

6.1

ns

t(Ø)

Static Phase Offset; NOTE 2, 4

PLL_SEL = 3.3V

-500

500

ps

tsk(o)

Output Skew; NOTE 3, 4

PLL_SEL = 0V

65

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 4

50

65

ps

t

L

PLL Lock Time

1mS

t

R

/ t

F

Output Rise/Fall Time

0.4

1

ns

odc

Output Duty Cycle

49

51

%

All parameters measured at f

MAX

unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V

DDO

/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal

when the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.

Measured at V

DDO

/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.