REVISION B 7/10/15

86004 DATA SHEET

5

15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/

LVTTL ZERO DELAY CLOCK BUFFER

DD

= V

DDA

= 3.3V±5%, V

DDO

DD

= V

DDA

= V

DDO

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Output Frequency

F_SEL = 0

31.25

62.5

MHz

F_SEL = 1

15.625

31.25

MHz

tp

LH

Propagation Delay, Low-to-High; NOTE 1

PLL_SEL = 0V,

Bypass Mode

4.25

6.25

ns

t(Ø)

Static Phase Offset; NOTE 2, 4

PLL_SEL = 2.5V

-500

500

ps

tsk(o)

Output Skew; NOTE 3, 4

PLL_SEL = 0V

65

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 4

65

ps

t

L

PLL Lock Time

1mS

t

R

/ t

F

Output Rise/Fall Time

0.4

1

ns

odc

Output Duty Cycle

48

52

%

All parameters measured at f

MAX

unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V

DDO

/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal

when the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.

Measured at V

DDO

/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f

MAX

Output Frequency

F_SEL = 0

31.25

62.5

MHz

F_SEL = 1

15.625

31.25

MHz

tp

LH

Propagation Delay, Low-to-High; NOTE 1

PLL_SEL = 0V,

Bypass Mode

4.5

6.5

ns

t(Ø)

Static Phase Offset; NOTE 2, 4

PLL_SEL = 2.5V

-500

500

ps

tsk(o)

Output Skew; NOTE 3, 4

PLL_SEL = 0V

65

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 4

70

ps

t

L

PLL Lock Time

1mS

t

R

/ t

F

Output Rise/Fall Time

0.4

1

ns

odc

Output Duty Cycle

48

52

%

All parameters measured at f

MAX

unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V

DDO

/2.

NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal

when the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.

Measured at V

DDO

/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.