15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/

LVTTL ZERO DELAY CLOCK BUFFER

86004 DATA SHEET

8

REVISION B 7/10/15

As in any high speed analog circuitry, the power supply

pins are vulnerable to random noise. The 86004 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

DD

, V

DDA

, and

V

DDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01μF bypass

capacitor should be connected to each V

DDA

.

10

Ω

V

DDA

10

μF

.01

μF

3.3V

.01

μF

V

DD

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1k

Ω resistor can be used.

All unused LVCMOS output can be left floating. We recommend that

there is no trace attached.

Figure 2 shows a schematic example of using an 86004. It is

recommended to have one decouple capacitor per power pin. Each

decoupling capacitor should be located as close as possible to the

power pin. The low pass filter R7, C11 and C16 for clean analog

supply should also be located as close to the V

VDD

Ro ~ 7 Ohm

LVCMOS

R4

100

U1

ICS86004

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Q1

GND

Q0

F_SEL

VDD

CLK

GND

VDDA

PLL_SEL

FB_IN

MR

VDDO

Q3

GND

Q2

VDDO

VDD

R3

1K

C11

0.01u

R2

43

VDD

Zo = 50

Zo = 50

R11

43

Serial Termination

VDD

R6

1K

Zo = 50

(U1-12)

VDD

C2

0.1uF

(U1-5)

Zo = 50

VDD

C16

10u

VDD=3.3V

R8

43

Parallel Termination

Zo = 50

R7

10

R1

43

VDD

C3

0.1uF

(U1-16)

C1

0.1uF

R5

100