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87002-02 Datasheet(PDF) 3 Page - Integrated Device Technology |
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87002-02 Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 16 page  1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 3 Rev C 7/13/15 87002-02 DATA SHEET Function Tables Table 3A. PLL Enable Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q0, Q1 0000 125 - 250 ÷1 0001 62.5 - 125 ÷1 0010 31.25 - 62.5 ÷1 0011 15.625 - 31.25 ÷1 0100 125 - 250 ÷2 0101 62.5 - 125 ÷2 0110 31.25 - 62.5 ÷2 0111 125 - 250 ÷4 1000 62.5 - 125 ÷4 1001 125 - 250 ÷8 1010 62.5 - 125 x2 1011 31.25 - 62.5 x2 1100 15.625 - 31.25 x2 1101 31.25 - 62.5 x4 1110 15.625 - 31.25 x4 1111 15.625 - 31.25 x8 |
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