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ICS8714004I Datasheet(PDF) 19 Page - Integrated Device Technology |
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ICS8714004I Datasheet(HTML) 19 Page - Integrated Device Technology |
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19 / 31 page  ICS8714004DKI REVISION A MARCH 24, 2014 19 ©2014 Integrated Device Technology, Inc. ICS8714004I Data Sheet FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 4A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. Figure 4A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 4C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 4E. CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 4B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 4F. CLK/nCLK Input Driven by a 3.3V MLVDS Driver R1 50 Ω R2 50 Ω 1.8V Zo = 50 Ω Zo = 50 Ω CLK nCLK 3.3V LVHSTL IDT LVHSTL Driver Differential Input 3.3V CLK nCLK 3.3V 3.3V LVPECL Differential Input HCSL *R3 *R4 CLK nCLK 3.3V 3.3V Differential Input CLK nCLK Differential Input LVPECL 3.3V Zo = 50 Ω Zo = 50 Ω 3.3V R1 50 Ω R2 50 Ω R2 50 Ω 3.3V R1 100 Ω LVDS CLK nCLK 3.3V Receiver Zo = 50 Ω Zo = 50 Ω 3.3V R1 100 Ω R2 100 Ω MLVDS CLK nCLK 3.3V Receiver Zo = 50 Ω Zo = 50 Ω |
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