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ICS8714004I Datasheet(PDF) 2 Page - Integrated Device Technology |
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ICS8714004I Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 31 page ICS8714004DKI REVISION A MARCH 24, 2014 2 ©2014 Integrated Device Technology, Inc. ICS8714004I Data Sheet FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet Block Diagram PDIV1:0 00 ÷4 (default) 01 ÷5 10 ÷8 11 ÷1 CLK nCLK PDIV0 PDIV1 FBI_DIV1:0 00 ÷1 01 ÷2 10 ÷4 11 ÷5 (default) FBIN nFBIN FBI_DIV0 FBI_DIV1 MLVDS nMLVDS PD PLL VCO Range 490-660MHz 0 1 OE_MLVDS PLL_SEL QDIV1 0 ÷4 (default) 1 ÷5 QDIV1 (PD) Q1 nQ1 QDIV2 0 ÷4 (default) 1 ÷5 QDIV2 (PD) Q2 nQ2 QDIV3 0 ÷4 (default) 1 ÷5 QDIV3 (PD) Q3 nQ3 QDIV0 0 ÷4 (default) 1 ÷5 QDIV0 (PD) Q0 nQ0 FBO_DIV 0 ÷4 (default) 1 ÷5 FBO_DIV (PD) FBOUT nFBOUT 2 OE[1:0] (PU, PU) Pull-up resistor (PU) on pin (power-up default is HIGH if not externally driven) Pull-down resistor (PD) on pin (power-up default is LOW if not externally driven) MR IREF Pullup/Pulldown Pullup Pullup Pullup Pullup/Pulldown Pulldown Pulldown Pulldown Pullup Pulldown Pulldown |
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