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ICS8714004I Datasheet(PDF) 22 Page - Integrated Device Technology |
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ICS8714004I Datasheet(HTML) 22 Page - Integrated Device Technology |
22 / 31 page ICS8714004DKI REVISION A MARCH 24, 2014 22 ©2014 Integrated Device Technology, Inc. ICS8714004I Data Sheet FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet Recommended Termination Figure 6A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™and HCSL output types. All traces should be 50 Ω impedance single-ended or 100Ω differential. Figure 6A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 6B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0 Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100 Ω differential. Figure 6B. Recommended Termination (where a point-to-point connection can be used) 0-0.2" PCI Expres s L1 L1 1-14" Driver Rs 0.5" Max L3 L4 L2 L2 49.9 +/- 5% 22 to 33 +/-5% Rt L3 L4 L5 0.5 - 3.5" L5 Connector PCI Expres s Add-in Card PCI Expres s 0-0.2" PCI Expres s 0-0.2" 0-18" L1 L1 Rs Driver 0.5" Max L3 L3 L2 L2 49.9 +/- 5% 0 to 33 0 to 33 Rt |
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