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ICS8714004I Datasheet(PDF) 24 Page - Integrated Device Technology |
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ICS8714004I Datasheet(HTML) 24 Page - Integrated Device Technology |
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24 / 31 page  ICS8714004DKI REVISION A MARCH 24, 2014 24 ©2014 Integrated Device Technology, Inc. ICS8714004I Data Sheet FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet Schematic Example Figure 7 (next page) shows an example ICS8714004I application schematic. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. Input and output terminations shown are also intended as examples only and may not represent the exact user configuration. In this particular schematic the MLVDS port is in output mode, configured by setting OE_MLVDS = 1. Since the zero delay function is local to the chip, the FBOUT to FBIN connection is a special case of a point to point PCIe link. The close proximity of these two ports means that the 33 series resistors are not necessary and the 49.9 termination resistors are to be placed at the FBIN port. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8714004I provides separate VDD and VDDA power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is highly recommended that the 0.1uF capacitors be placed on the device side of the PCB as close to the power pins as possible. This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite bead, 10uf and 0.1uF capacitors connected to 3.3V can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. |
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