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ICS8714004I Datasheet(PDF) 25 Page - Integrated Device Technology |
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ICS8714004I Datasheet(HTML) 25 Page - Integrated Device Technology |
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25 / 31 page  ICS8714004DKI REVISION A MARCH 24, 2014 25 ©2014 Integrated Device Technology, Inc. ICS8714004I Data Sheet FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet Figure 7. ICS8714004I Schematic Example LVDS Driv er Zo = 50 Ohm Zo = 50 Ohm R1 100 VDDA C1 0.1uF 3.3V C2 10uF FB1 BLM18BB221SN1 1 2 C3 10uF Place each 0.1uF bypass cap directly adjacent to its corresponding VDD or VDDA pin. VDD VDDA C5 0. 1uF C4 0. 1uF VDD C6 0. 1uF Zo = 50 Zo = 50 1" t o 14 " 0" t o 18 " R2 33 0. 5" t o 3. 5" PCI E xpress Add-In Card R3 33 HCS L Terminati on Optional C7 0. 1uF PCI E xpress Point-to-Point Connecti on R4 50 Zo = 50 Zo = 50 R5 50 R6 33 C8 0. 1uF C9 0.1uF Zo = 50 R7 50 C10 0.1uF Zo = 50 R8 50 C11 0.1uF R9 33 HCSL_Rec eiv er + - HCSL_Rec eiv er + - VDD VDD To L ogic In put pins VDD RU2 Not Ins tall RU1 1K RD2 1K To L ogic In put pins RD1 Not Ins tall Logic Control Input E xamples Set Logi c Input to '1' Set Logi c Input to '0' R11 475 R12 49.9 R13 49.9 OE0 OE_MLVDS MR OE1 FBI_DIV0 FBI_DIV1 PLL_SEL PDI V0 FBO_DIV QDIV1 QDIV0 PDI V1 QDIV3 QDIV2 CLK nCLK FB2 BLM18BB221SN1 1 2 To MLVDS bus OE_MLVDS = 1 to select MLVDS output U1 OE_MLVDS 2 MLVDS 3 nMLVDS 4 PLL_SEL 5 FBO_DIV 6 MR 7 OE0 8 OE1 9 FBI_DIV0 12 FBI_DIV1 13 FBIN 15 nFBIN 14 QDIV0 17 QDIV1 18 QDIV2 19 QDIV3 20 IREF 21 CLK 37 nCLK 38 PDIV0 39 PDIV1 40 nFBOUT 23 FBOUT 24 nQ3 25 Q3 26 nQ2 28 Q2 29 nQ1 31 Q1 32 nQ0 33 Q0 34 VDDA 36 MLVDS nMLVDS |
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