ICS8714004I datasheet(27/31 Pages) IDT

Part #	ICS8714004I

Description	Output frequency range

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Manufacturer	IDT [Integrated Device Technology]

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ICS8714004DKI REVISION A MARCH 24, 2014

27

ICS8714004I Data Sheet

FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet

3. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.

HCSL output driver circuit and termination are shown in Figure 8.

Figure 8. HCSL Driver Circuit and Termination

HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,

use the following equations which assume a 50

 load to ground.

The highest power dissipation occurs when VDD_MAX.

Power

= (VDD_MAX – VOUT) * IOUT,

since VOUT = IOUT * RL

= (VDD_MAX – IOUT * RL) * IOUT

= (3.465V – 17mA * 50

) * 17mA

Total Power Dissipation per output pair = 44.5mW

VDD

VOUT

RL

50



IC

IOUT = 17mA

RREF =

475

 ± 1%

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