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ICS8714004I Datasheet(PDF) 29 Page - Integrated Device Technology |
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ICS8714004I Datasheet(HTML) 29 Page - Integrated Device Technology |
29 / 31 page ICS8714004DKI REVISION A MARCH 24, 2014 29 ©2014 Integrated Device Technology, Inc. ICS8714004I Data Sheet FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet Package Outline and Package Dimensions Package Outline - K Suffix for 40 Lead VFQFN Table 8. Package Dimensions Reference Document: JEDEC Publication 95, MO-220 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pin-out are shown on the front page. The package dimensions are in Table 8. To p View Ind exArea D Chamfer 4x 0.6 x 0.6 max OPTIONAL Anvil Singula tion A 0. 08 C C A3 A1 S eating Plan e E2 E2 2 L (N -1)x e (R ef.) (Ref.) N & N Even N e D2 2 D2 (Ref.) N & N Odd 1 2 e 2 (Ty p.) If N & N are Even (N -1)x e (Re f.) b Th er mal Ba se N OR Anvil Singulation or Sawn Singulation N-1 N CHAMFER 1 2 N-1 1 2 N RADIUS 4 4 Bottom View w/Type C ID Bottom View w/Type A ID There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) JEDEC Variation: VJJD-2/-5 All Dimensions in Millimeters Symbol Minimum Maximum N 40 A 0.80 1.00 A1 00.05 A3 0.25 Ref. b 0.18 0.30 ND & NE 10 D & E 6.00 Basic D2 & E2 4.65 4.65 e 0.50 Basic L 0.30 0.50 |
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