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TLF80511EJ Datasheet(PDF) 7 Page - Infineon Technologies AG

Part # TLF80511EJ
Description  Low Dropout Linear Fixed Voltage Regulator
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLF80511EJ Datasheet(HTML) 7 Page - Infineon Technologies AG

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Data Sheet
7
Rev. 1.0, 2014-11-17
TLF80511EJ
General Product Characteristics
4.2
Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 2
Functional Range
Parameter
Symbol
Values
Unit Note / Test Condition Number
Min.
Typ.
Max.
Input Voltage Range for Normal
Operation
V
I
V
Q,nom + Vdr –40
V
Extended Input Voltage Range
V
I,ext
3.3
40
V
T
j > 25 °C
1)
1) Between min. value and
V
Q,nom + Vdr: VQ = VI - Vdr. Below min. value: VQ =0V
Output Capacitor’s
Requirements for Stability
C
Q
1–
µF
2)
2) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
Output Capacitor’s
Requirements for Stability
ESR(C
Q) ––
5
3)
3) relevant ESR value at
f =10kHz
Junction Temperature
T
j
-40
150
°C
Table 3
Thermal Resistance
Parameter
Symbol
Values
Unit
Note / Test Condition Number
Min.
Typ.
Max.
Package Version PG-DSO8-EP
Junction to Case1)
1) Not subject to production test, specified by design
R
thJC
–11
K/W
Junction to Ambient1)
R
thJA
–41
K/W
2)
2) Specified
R
thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Junction to Ambient1)
R
thJA
152
K/W
footprint only3)
3) Specified
R
thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Junction to Ambient1)
R
thJA
67
K/W
300 mm2 heatsink
area on PCB3)
Junction to Ambient1)
R
thJA
56
K/W
600 mm2 heatsink
area on PCB3)


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