PIC17LC44-08SLASHP datasheet(223/240 Pages) MICROCHIP

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DS30412C-page 223

PIC17C4X

APPENDIX F: ERRATA FOR

PIC17C42 SILICON

The PIC17C42 devices that you have received have the

following anomalies. At present there is no intention for

future revisions to the present PIC17C42 silicon. If

these cause issues for the application, it is recom-

mended that you select the PIC17C42A device.

When the Oscillator Start-Up Timer (OST) is

enabled (in LF or XT oscillator modes), any inter-

rupt that wakes the processor may cause a WDT

reset. This occurs when the WDT is greater than

or equal to 50% time-out period when the SLEEP

instruction is executed. This will not occur in

either the EC or RC oscillator modes.

Work-arounds

Always ensure that the CLRWDT instruction is

executed before the WDT increments past 50%

of the WDT period. This will keep the “false”

WDT reset from occurring.

When using the WDT as a normal timer (WDT

disabled), ensure that the WDT is less than or

equal to 50% time-out period when the SLEEP

instruction is executed. This can be done by

monitoring the TO bit for changing state from set

to clear. Example 1 shows putting the PIC17C42

to sleep.

EXAMPLE F-1:

PIC17C42 TO SLEEP

BTFSS

CPUSTA, TO

; TO = 0?

CLRWDT

; YES, WDT = 0

LOOP

BTFSC

CPUSTA, TO

; WDT rollover?

GOTO

LOOP

; NO, Wait

SLEEP

; YES, goto Sleep

When the clock source of Timer1 or Timer2 is

selected to external clock, the overﬂow interrupt

ﬂag will be set twice, once when the timer equals

the period, and again when the timer value is

reset to 0h. If the latency to clear TMRxIF is

greater than the time to the next clock pulse, no

problems will be noticed. If the latency is less

than the time to the next timer clock pulse, the

interrupt will be serviced twice.

Work-arounds

Ensure that the timer has rolled over to 0h before

clearing the ﬂag bit.

Clear the timer in software. Clearing the timer in

software causes the period to be one count less

than expected.

Note:

New designs should use the PIC17C42A.

Design considerations

The device must not be operated outside of the speci-

ﬁed voltage range. An external reset circuit must be

used to ensure the device is in reset when a brown-out

occurs or the VDD rise time is too long. Failure to

ensure that the device is in reset when device voltage

is out of speciﬁcation may cause the device to lock-up

and ignore the MCLR pin.

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