ATmega16 datasheet(102/315 Pages) ATMEL

102 / 315 page

102

ATmega16(L)

2466E–AVR–10/02

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be

set to high for non-inverted PWM mode. For inverted PWM the output will have the

opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and

COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

Timer/Counter Timing

Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T1) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when interrupt flags are set, and when the OCR1x Register is updated with the

OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing

diagram for the setting of OCF1x.

Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, No Prescaling

Figure 50 shows the same timing data, but with the prescaler enabled.

Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f

clk_I/O/8)

clk

(clk

I/O/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

clk

I/O

clk

(clk

I/O/8)

ATMEGA16 Datasheet(PDF) 102 Page - ATMEL Corporation

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