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ATMEGA16 Datasheet(PDF) 134 Page - ATMEL Corporation

Part # ATMEGA16
Description  8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash
PDF  315 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATMEGA16 Datasheet(HTML) 134 Page - ATMEL Corporation

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134
ATmega16(L)
2466E–AVR–10/02
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 67 and Figure 68 for an example. The CPOL func-
tionality is summarized below:
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 67 and Figure 68 for an example.
The CPHA functionality is summarized below:
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f
osc is shown in the following table:
SPI Status Register – SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE
in SPCR is set and global interrupts are enabled. If SS is an input and is driven low
when the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by
Table 56. CPOL Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
Table 57. CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1Setup
Sample
Table 58. Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
SCK Frequency
00
0
f
osc/4
00
1
f
osc/16
01
0
f
osc/64
01
1
f
osc/128
10
0
f
osc/2
10
1
f
osc/8
11
0
f
osc/32
11
1
f
osc/64
Bit
765
432
10
SPIF
WCOL
–
–
–
–
–
SPI2X
SPSR
Read/Write
RR
RRR
RR
R/W
Initial Value
0
0
0
0
0
0
0
0



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