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ATMEGA16 Datasheet(PDF) 214 Page - ATMEL Corporation |
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ATMEGA16 Datasheet(HTML) 214 Page - ATMEL Corporation |
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214 / 315 page ![]() 214 ATmega16(L) 2466E–AVR–10/02 • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. The ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. If differ- ential channels are used, the result is presented in two’s complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse- quently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. Table 84. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Bit 151413 12 11 10 9 8 ––––– – ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 76543 210 Read/Write RRRRRRR R RRRRRRR R Initial Value 00000 000 00000 000 Bit 151413 12 11 10 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 – – – – – – ADCL 76543 210 Read/Write RRRRRRR R RRRRRRR R Initial Value 00000 000 00000 000 |
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