ATmega16 datasheet(234/315 Pages) ATMEL

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234

ATmega16(L)

2466E–AVR–10/02

If the ADC is not to be used during scan, the recommended input values from Table 91

should be used. The user is recommended not to use the Differential Gain stages dur-

ing scan. Switch-cap based gain stages require fast operation and accurate timing

which is difficult to obtain when used in a scan chain. Details concerning operations of

the differential gain stage is therefore not provided. For the same reason, the ADC High

Speed mode (ADHSM) bit does not make any sense during Boundary-scan operation.

The AVR ADC is based on the analog circuitry shown in Figure 123 with a successive

approximation algorithm implemented in the digital logic. When used in Boundary-scan,

the problem is usually to ensure that an applied analog voltage is measured within some

limits. This can easily be done without running a successive approximation algorithm:

apply the lower limit on the digital DAC[9:0] lines, make sure the output from the com-

parator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the

output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are

shared with a digital port pin as well.

When using the ADC, remember the following:

•

The Port Pin for the ADC channel in use must be configured to be an input with pull-

up disabled to avoid signal contention.

•

In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed

when enabling the ADC. The user is advised to wait at least 200 ns after enabling

the ADC before controlling/observing any ADC signal, or perform a dummy

conversion before using the first result.

•

The DAC values must be stable at the midpoint value 0x200 when having the HOLD

signal low (Sample mode).

As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3

when the power supply is 5.0V and AREF is externally connected to VCC.

The recommended values from Table 91 are used unless other values are given in the

algorithm in Table 92. Only the DAC and Port Pin values of the Scan-chain are shown.

The column “Actions” describes what JTAG instruction to be used before filling the

Boundary-scan register with the succeeding columns. The verification should be done

on the data scanned out when scanning in the data on the same row in the table.

The lower limit is:

1024 1.5V 0,95 5V

⁄

⋅⋅

291

0x123

The upper limit is:

1024 1.5V 1.05 5V

⁄

⋅⋅

323

0x143

ATMEGA16 Datasheet(PDF) 234 Page - ATMEL Corporation

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