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TAS5760LD Datasheet(PDF) 6 Page - Texas Instruments |
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TAS5760LD Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 68 page  TAS5760LD SLOS781A – JULY 2013 – REVISED JULY 2015 www.ti.com Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT RHP Headphone Load 16 Ω RLD Line Driver Load 1 Ω RSPK (BTL) Minimum Speaker Load in BTL Mode 4 Ω RSPK (PBTL) Minimum Speaker Load in PBTL Mode 2 Ω 7.4 Thermal Information TAS5760LD THERMAL METRIC(1) DCA [HTSSOP] DCA [HTSSOP] UNIT 48 PIN(2) 48 PIN(3) θJA Junction-to-ambient thermal resistance 60.3 30.2 °C/W θJC(top) Junction-to-case (top) thermal resistance 16 14.3 °C/W θJB Junction-to-board thermal resistance 12 12.7 °C/W ψJT Junction-to-top characterization parameter 0.4 0.6 °C/W ψJB Junction-to-board characterization parameter 11.9 12.7 °C/W θJC(bottom) Junction-to-case (bottom) thermal resistance 0.8 0.7 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) JEDEC Standard 2 Layer Board (3) JEDEC Standard 4 Layer Board 7.5 Digital I/O Pins over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Logic HIGH threshold for DVDD All digital pins except for VIH1 70 %DVDD Referenced Digital Inputs DR_MUTE Input Logic LOW threshold for DVDD All digital pins except for VIL1 30 %DVDD Referenced Digital Inputs DR_MUTE All digital pins except for IIH1 Input Logic HIGH Current Level 15 µA DR_MUTE All digital pins except for IIL1 Input Logic LOW Current Level –15 µA DR_MUTE VOH Output Logic HIGH Voltage Level IOH = 2 mA 90 %DVDD VOL Output Logic LOW Voltage Level IOH = -2 mA 10 %DVDD Input Logic HIGH threshold for DRVDD VIH2 For DR_MUTE Pin 60 %DRVDD Referenced Digital Inputs Input Logic LOW threshold for DRVDD VIL2 For DR_MUTE Pin 40 %DRVDD Referenced Digital Inputs IIH2 Input Logic HIGH Current Level For DR_MUTE Pin 1 µA IIL2 Input Logic LOW Current Level For DR_MUTE Pin –1 µA 7.6 Master Clock over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DMCLK Allowable MCLK Duty Cycle 45% 50% 55% MCLK Input Frequency 25 MHz Supported single-speed MCLK Values: 64, 128, 192, 256, 384, 64 512 fMCLK Frequencies and 512 x fs Supported double-speed MCLK Values: 64, 128, and 256 64 256 Frequencies 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TAS5760LD |
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