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TAS5760LDAPR Datasheet(PDF) 24 Page - Texas Instruments

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Part # TAS5760LDAPR
Description  General-Purpose I2S Input Class-D Amplifier
Download  77 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TAS5760LDAPR Datasheet(HTML) 24 Page - Texas Instruments

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Digital to PWM
Conversion
011010..
.
Digital
Comparator
Mux
22 Bit Audio Sample in Data Path
20 Bit Digital Clipper Level in Control Port
Digital Clipper
TAS5760L
SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015
www.ti.com
Feature Description (continued)
9.3.2.1.3
Right-Justified
Right-justified (RJ) timing also uses LRCK to define when the data being transmitted is for the left channel and
when it is for the right channel. LRCK is HIGH for the left channel and LOW for the right channel. A bit clock
running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock
periods (for 24-bit data) after LRCK toggles. In RJ mode the LSB of data is always clocked by the last bit clock
before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The TAS5760L
pads unused leading data-bit positions in the left/right frame with zeros before presenting the digital word to the
audio signal path.
9.3.2.2 DC Blocking Filter
Excessive DC content in the audio signal can damage loudspeakers and even small amounts of DC offset in the
signal path cause cause audible artifacts when muting and unmuting the speaker amplifier. For these reasons,
the amplifier employs two separate DC blocking methods for the speaker amplifier. The first is a high-pass filter
provided at the front of the data path to remove any DC from incoming audio data before it is presented to the
audio path. The –3 dB corner frequencies for the filter are specified in the speaker amplifier electrical
characteristics table. In Hardware Control mode, the DC blocking filter is active and cannot be disabled. In
Software Control mode, the filter can be bypassed by writing a 1 to bit 7 of register 0x02. The second method is
a DC detection circuit that will shutdown the power stage and issue a latching fault if DC is found to be present
on the output due to some internal error of the device. This DC Error (DCE) protection is discussed in the
Protection Circuitry section below.
9.3.2.3 Digital Boost and Volume Control
Following the high-pass filter, a digital boost block is included to provide additional digital gain if required for a
given application as well as to set an appropriate clipping point for a given GAIN[1:0] pin configuration when in
Hardware Control mode. The digital boost block defaults to +6dB when the device is in Hardware Mode. In most
use cases, the digital boost block will remain unchanged when operating the device in Software Control mode, as
the volume control offers sufficient digital gain for most applications. The TAS5760L's digital volume control
operates from Mute to 24 dB, in steps of 0.5 dB. The equation below illustrates how to set the 8-bit volume
control register at address 0x04:
DVC [Hex Value] = 0xCF + (DVC [dB] / 0.5 [dB] )
(1)
Transitions between volume settings will occur at a rate of 0.5 dB every 8 LRCK cycles to ensure no audible
artifacts occur during volume changes. This volume fade feature can be disabled via Bit 7 of the Volume Control
Configuration Register.
9.3.2.4 Digital Clipper
A digital clipper is integrated in the oversampled domain to provide a component-free method to set the clip point
of the speaker amplifier. Through the "Digital Clipper Level x" controls in the I²C control port, the point at which
the oversampled digital path clips can be set directly, which in turns sets the 10% THD+N operating point of the
amplifier. This is useful for applications in which a single system is designed for use in several end applications
that have different power rating specifications. Its place in the oversampled domain ensures that the digital
clipper is acoustically appealing and reduces or eliminates tones which would otherwise foldback into the audio
band during clipping events. Figure 39 shows a block diagram of the digital clipper.
Figure 39. Digital Clipper Simplified Block Diagram
24
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Product Folder Links: TAS5760L


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