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STM32F756VG Datasheet(PDF) 132 Page - STMicroelectronics

Part # STM32F756VG
Description  Up to 25 communication interfaces
PDF  228 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F756VG Datasheet(HTML) 132 Page - STMicroelectronics

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Electrical characteristics
STM32F756xx
132/228
DocID027589 Rev 4
5.3.12
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 52: EMI characteristics). It is available only on the main PLL.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
fPLL_IN and fMod must be expressed in Hz.
As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
Jitter(3)
Master SAI clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS
-
90
-
peak
to
peak
-
±280
-
ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90
-
ps
FS clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-400
-
ps
IDD(PLLSAI)(4)
PLLSAI power consumption on
VDD
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
IDDA(PLLSAI)(4)
PLLSAI power consumption on
VDDA
VCO freq = 100 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 45. PLLISAI characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 46. SSCG parameters constraint
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
Modulation frequency
-
-
10
KHz
md
Peak modulation depth
0.25
-
2
%
MODEPER * INCSTEP
-
-
-
215
− 1-
1. Guaranteed by design.
MODEPER
round fPLL_IN
4fMod
×
()
[]
=
MODEPER
round 10
6
410
3
×
()
[]
250
==



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