List of figures

VN7007AH

List of figures

Figure 1: Block diagram ..............................................................................................................................5

Figure 2: Configuration diagram (top view).................................................................................................6

Figure 3: Current and voltage conventions.................................................................................................7

Figure 4: IOUT/ISENSE versus IOUT.......................................................................................................13

Figure 5: Current sense precision vs. IOUT .............................................................................................13

Figure 6: Switching times and Pulse skew ...............................................................................................14

Figure 7: tDSTKON...................................................................................................................................14

Figure 8: OFF-state output current ...........................................................................................................15

Figure 9: Standby current .........................................................................................................................15

Figure 10: IGND(ON) vs Tcase ................................................................................................................16

Figure 11: Logic Input high level voltage ..................................................................................................16

Figure 12: Logic Input low level voltage....................................................................................................16

Figure 13: High level logic input current ...................................................................................................16

Figure 14: Low level logic input current ....................................................................................................16

Figure 15: Logic Input hysteresis voltage .................................................................................................16

Figure 16: Undervoltage shutdown...........................................................................................................17

Figure 17: On-state resistance vs Tcase ..................................................................................................17

Figure 18: On-state resistance vs VCC ....................................................................................................17

Figure 19: Turn-on voltage slope ..............................................................................................................17

Figure 20: Turn-off voltage slope ..............................................................................................................17

Figure 21: Won vs Tcase ..........................................................................................................................17

Figure 22: Woff vs Tcase ..........................................................................................................................18

Figure 23: ILIMH vs. Tcase.......................................................................................................................18

Figure 24: Turn-off output voltage clamp..................................................................................................18

Figure 25: OFF-state open-load voltage detection threshold ...................................................................18

Figure 26: Vsense clamp vs. Tcase..........................................................................................................18

Figure 27: Vsenseh vs. Tcase ..................................................................................................................18

Figure 28: Application diagram .................................................................................................................20

Figure 29: Simplified internal structure .....................................................................................................20

Figure 30: CurrentSense and diagnostic – block diagram........................................................................22

Figure 31: CurrentSense block diagram ...................................................................................................23

Figure 32: Analogue HSD – open-load detection in off-state ...................................................................24

Figure 33: Open-load / short to VCC condition.........................................................................................25

Figure 34: Maximum turn off current versus inductance ..........................................................................27

Figure 35: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5)......................................................28

Figure 36: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7) .....................................................28

Figure 37: Rthj-amb vs PCB copper area in open box free air conditions ...............................................29

Figure 38: Octapak thermal impedance junction ambient single pulse ....................................................29

Figure 39: Thermal fitting model for Octapak ...........................................................................................30

Figure 40: Octapak package dimensions .................................................................................................31

Figure 41: Octapack reel 13" ....................................................................................................................33

Figure 42: Octapak carrier tape ................................................................................................................34

Figure 43: Octapak schematic drawing of leader and trailer tape ............................................................34

Figure 44: Octapak marking information...................................................................................................35

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