MB9BF412R datasheet(105/121 Pages) SPANSION

105 / 121 page

D a t a S h e e t

102

MB9B410R-DS706-00026-3v0-E, March 11, 2015

CONFIDENTIAL

12-bit A/D Converter

・Electrical Characteristics for the A/D Converter

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)

Parameter

Symbol

name

Value

Unit

Remarks

Min

Typ

Max

Resolution

bit

Integral Nonlinearity

± 4.0

± 4.5

LSB

AVRH =

2.7 V to 5.5 V

Differential Nonlinearity

± 2.3

± 2.5

LSB

Zero transition voltage

VZT

ANxx

± 10

± 15

Full-scale transition

voltage

VFST

ANxx

AVRH ± 10 AVRH ± 15 mV

Conversion time

1.0*

μs

AVCC ≥ 4.5 V

1.2*

AVCC < 4.5 V

Sampling time

AVCC ≥ 4.5 V

AVCC < 4.5 V

Compare clock cycle*

tCCK

2000

AVCC ≥ 4.5 V

AVCC < 4.5 V

State transition time to

operation permission

tSTT

1.0

μs

Analog input capacity

CAIN

12.9

Analog input resistance

RAIN

kΩ

AVCC ≥ 4.5 V

3.8

AVCC < 4.5 V

Interchannel disparity

LSB

Analog port input current

ANxx

μA

Analog input voltage

ANxx

AVSS

AVRH

Reference voltage

AVRH

2.7

AVCC

*1: Conversion time is the value of sampling time (tS) + compare time (tC).

The condition of the minimum conversion time is the following.

AVCC ≥ 4.5 V, HCLK=120 Hz

sampling time: 300 ns, compare time: 700 ns

AVCC < 4.5 V, HCLK=120 Hz

sampling time: 500 ns, compare time: 700 ns

Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK).

For setting*

4 of sampling time and compare clock cycle, see "CHAPTER 1-1: 12-bit A/D Converter" in

"FM3 Family PERIPHERAL MANUAL Analog Macro Part".

A/D Converter register is set at APB bus clock timing. Sampling and compare clock is set at Base clock

(HCLK).

About the APB bus number which the A/D Converter is connected to, see "■ Block Diagram" in this data

sheet.

*2: A necessary sampling time changes by external impedance.

Ensure that it set the sampling time to satisfy (Equation 1).

*3: Compare time (tC) is the value of (Equation 2).

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