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ADIS16488A Datasheet(PDF) 5 Page - Analog Devices |
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ADIS16488A Datasheet(HTML) 5 Page - Analog Devices |
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5 / 35 page  Product Overview Online Documentation Design Resources Discussion Sample & Buy Data Sheet ADIS16488A Rev. C | Page 5 of 35 TIMING SPECIFICATIONS TC = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. Normal Mode Parameter Description Min1 Typ Max1 Unit fSCLK Serial clock 0.01 15 MHz tSTALL2 Stall period between data 2 µs tCLS Serial clock low period 31 ns tCHS Serial clock high period 31 ns t CS Chip select to clock edge 32 ns tDAV DOUT valid after SCLK edge 10 ns tDSU DIN setup time beforeSCLK risingedge 2 ns tDHD DIN hold time after SCLK rising edge 2 ns tDR, tDF DOUT rise/fall times, ≤100 pF loading 3 8 ns tDSOE CS assertion to data out active 0 11 ns tHD SCLK edge to data out invalid 0 ns tSFS Last SCLK edge to CS deassertion 32 ns tDSHI CS deassertion to data out high impedance 0 9 ns t1 Input sync pulse width 5 µs t2 Input sync to data invalid 490 µs t3 Input sync period 417 µs 1 Guaranteed by design and characterization, but not tested in production. 2 See Table 3 for exceptions to the stall time rating Table 3. Register SpecificStall Times Register Function Minimum Stall Time (μs) FNCTIO_CTRL Configure DIOx functions 15 FLTR_BNK0 Enable/select FIR filter banks 10 FLTR_BNK1 Enable/select FIR filter banks 10 NULL_CFG Configure autonull bias function 10 GLOB_CMD[1] Self-test 12,000 GLOB_CMD[2] Flash memory test 50,000 GLOB_CMD[3] Flash memory update 375,000 GLOB_CMD[6] Factory calibration restore 75,000 GLOB_CMD[7] Software reset 120,000 |
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