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ADIS16488A Datasheet(PDF) 10 Page - Analog Devices |
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ADIS16488A Datasheet(HTML) 10 Page - Analog Devices |
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10 / 35 page  Product Overview Online Documentation Design Resources Discussion Sample & Buy ADIS16488A Data Sheet Rev. C | Page 10 of 35 THEORY OF OPERATION The ADIS16488A is an autonomous sensorsystem that self starts when it has a valid power supply. Afterrunning throughits initialization process, it begins sampling, processing, and loading calibrated sensordata into the outputregisters, which are accessibleusingtheSPIport.TheSPIporttypicallyconnects to a compatible port on an embedded processor, using the connec- tions as shown in Figure11. The fourSPIsignalsfacilitatesynchronous, serial datacommuni- cation. Connect the reset line (RST)to VDD or do not connect it to anything for normal operation. The factory default configuration providesuserswith a data readysignal on the DIO2 pin, which pulses high when new data is available in the output data registers. SYSTEM PROCESSOR SPI MASTER SCLK CS DIN DOUT SCLK SS MOSI MISO +3.3V IRQ DIO2 VDD I/O LINES ARE COMPATIBLE WITH 3.3V LOGIC LEVELS 10 6 3 5 4 9 11 12 23 13 14 15 ADIS16488A Figure 11. Electrical Connection Diagram Table 7. GenericMaster Processor PinNames and Functions Mnemonic Function SS Slave select IRQ Interrupt request MOSI Master output, slave input MISO Master input, slave output SCLK Serial clock Embedded processorstypicallyusecontrol registersto configure their serial ports for communicating with SPIslave devices, such as the ADIS16488A. Table 8 provides a list of settings describing the SPI protocol of the ADIS16488A. The initializa- tion routine of the master processor typically establishesthese settingsusing firmware commands to write theminto its serial control registers. Table 8. GenericMaster Processor SPI Settings Processor Setting Description Master The ADIS16488A operates as a slave SCLK ≤ 15 MHz Maximum serial clock rate SPI Mode 3 CPOL = 1 (polarity), and CPHA = 1 (phase) MSB-First Mode Bit sequence 16-Bit Mode Shift register/data length REGISTER STRUCTURE The register structureand SPIport providea bridge between the sensor processing system and an external, master processor. It contains both output data andcontrol registers. The output data registersincludethelatestsensor data, areal-timeclock, error flags, alarm flags, and identification data. The control registers include sample rate, filtering, input/output,alarms, calibration, and diagnosticconfiguration options. All communication between the ADIS16488A and an external processorinvolves either reading or writing to one of the user registers. DSP OUTPUT REGISTERS CONTROL REGISTERS TRIAXIS GYRO TRIAXIS MAGN BARO TEMP SENSOR CONTROLLER TRIAXIS ACCEL Figure 12. Basic Operation The register structureuses a paged addressing schemethat is composed of 13 pages, with each pagecontaining 64 register locations. Each register is 16 bits wide, with each byte having its own unique addresswithin the memory mapof that page. The SPI port has access to one page at a time, using the bit sequence shown in Figure 13. Select the page to activate for SPIaccess by writing its code to the PAGE_ID register. Read the PAGE_IDregister to determine which page is currently active. Table 9 displays the PAGE_ID contents foreach page,together withtheirbasicfunctions. The PAGE_ID registeris locatedat Address0x00 on every page. Table 9. User Register Page Assignments Page PAGE_ID Function 0 0x00 Output data, clock, identification 1 0x01 Reserved 2 0x02 Calibration 3 0x03 Control: sample rate, filtering, input/output, alarms 4 0x04 Serial number 5 0x05 FIR Filter Bank A, Coefficient 0 to Coefficient 59 6 0x06 FIR Filter Bank A, Coefficient 60 to Coefficient 119 7 0x07 FIR Filter Bank B, Coefficient 0 to Coefficient 59 8 0x08 FIR Filter Bank B, Coefficient 60 to Coefficient 119 9 0x09 FIR Filter Bank C, Coefficient 0 to Coefficient 59 10 0x0A FIR Filter Bank C, Coefficient 60 to Coefficient 119 11 0x0B FIR Filter Bank D, Coefficient 0 to Coefficient 59 12 0x0C FIR Filter Bank D, Coefficient 60 to Coefficient 119 SPI COMMUNICATION If the previouscommandwasa read request, theSPIport supports full duplex communication,which enablesexternal processorsto write to DIN while reading DOUT (see Figure13). Figure 13 provides a guideline for the bit coding on both DIN and DOUT. |
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