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Data Sheet

ADIS16488A

Rev. C | Page 11 of 35

R/W

R/W

A6

A5

A4

A3

A2

A1

A0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CS

SCLK

DIN

DOUT

A6

A5

D13

D14

D15

NOTES

1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.

2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE

FOR OTHER DEVICES.

Figure 13. SPI Communication Bit Sequence

DEVICE CONFIGURATION

The SPI provides write access tothecontrol registers,one byteat

a time, usingthebitassignments shownin Figure 13. Each register

has 16 bits, where Bits[7:0]represent the lower address (listed in

Table 10)and Bits[15:8] represent the upper address. Write to

the lower byte of a register first, followed by a write to its upper

byte (the only register that changes with a single write to its

lower byte is the PAGE_ID register).

For a write command, the first bit in theDINsequence is setto 1.

AddressBits[A6:A0]representthetarget address,andData

CommandBits[DC7:DC0]representthe data being written to the

location. Figure 14 provides an exampleof writing 0x03 to

Address0x00 (PAGE_ID[7:0])usingDIN = 0x8003. This write

command activatesthe control pagefor SPIaccess.

SCLK

CS

DIN

DIN = 1000 0000 0000 0011 = 0x8003, WRITES 0x03 TO ADDRESS 0x00

Figure 14. SPI Sequence for Activating the Control Page (DIN = 0x8003)

Dual Memory Structure

Writing configuration data toa control registerupdatesits SRAM

contents,whicharevolatile.Afteroptimizingeach relevant control

register settingin a system, usethemanual flash updatecommand,

which is located in GLOB_CMD[3]on Page3 of the register map.

Activatethemanual flash updatecommandbyturning toPage3

(DIN = 0x8003)andsetting GLOB_CMD[3]= 1 (DIN= 0x8208,

then DIN =0x8300).For a flash memory update, ensurethatthe

powersupplyis within specification fortheentireprocessing time

(see Table1). Table10 provides a memory mapforall oftheuser

registers, which includesa column offlashbackupinformation. A

yes in this columnindicatesthat a registerhas a mirror locationin

flash and, when backed up properly, automatically restores itself

during startup or after a reset. Figure15 providesa diagram of

the dual memory structurethat supports all device operations

and stores critical user settings.

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

MANUAL

FLASH

BACKUP

START-UP

RESET

VOLATILE

SRAM

SPI ACCESS

Figure 15. SRAM and Flash Memory Diagram

READING SENSOR DATA

The ADIS16488A automatically starts up and activates Page0

for data register access. Write 0x00 to the PAGE_ID register

(DIN = 0x8000) to activate Page 0 for data access after accessing

any other page.

A single register read requires two 16-bit SPIcycles. The first

cycle requeststhecontentsof a register usingthebit assignmentsin

Figure 13, and then the register contentsfollow DOUT during

the second sequence.

The first bit in a DIN command is zero, followedby either the

upper or lower address forthe register. The last eight bits are

don’t care, but the SPIrequires the full set of 16 SCLKs to

receive the request.

Figure 16 includes two register reads in succession, which starts

with DIN = 0x1A00, torequest the contents of theZ_GYRO_OUT

register, and follows with 0x1800, to request the contents of the

Z_GYRO_LOWregister.

DIN

DOUT

0x1A00

0x1800

NEXT

ADDRESS

Z_GYRO_OUT

Z_GYRO_LOW

Figure 16. SPI Read Example

Figure 17 providesan example of the fourSPIsignals when reading

PROD_IDin a repeating pattern. This is aneffectivepattern touse

for troubleshooting theSPIinterfacesetup and communications

becausethe contents of PROD_IDarepredefinedand stable.

SCLK

CS

DIN

DOUT

DOUT = 0100 0000 0110 1000 = 0x4068 = 16,488 (PROD_ID)

DIN = 0111 1110 0000 0000 = 0x7E00

Figure 17. SPI Read Example, Second 16-Bit Sequence