Data Sheet

ADIS16485

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

FLASH MEMORY

100,000

Cycles

20

Years

Time until data is available

Power-On, Start-Up Time

400 ± 160

ms

400 ± 160

ms

Sleep Mode Recovery Time

500

µs

Flash Memory Update Time

900

ms

Flash Memory Test Time

66

ms

Automatic Self Test Time

Using internal clock, 100 SPS

12

ms

CONVERSION RATE

2.46

kSPS

Initial Clock Accuracy

0.02

%

Temperature Coefficient

40

ppm/°C

0.7

2.4

kHz

POWER SUPPLY, VDD

Operating voltage range

3.0

3.6

V

Normal mode, VDD = 3.3 V, µ ± σ

197

mA

Sleep mode, VDD = 3.3 V

12.2

mA

Power-down mode, VDD = 3.3 V

37

µA

POWER SUPPLY, VDDRTC

Operating voltage range

3.0

3.6

V

Real-Time Clock Supply Current

Normal mode, VDDRTC = 3.3 V

13

µA

1

The repeatability specifications represent analytical projections that are based off of the following drift contributions and conditions: temperature hysteresis (−40°C to

+85°C), electronics drift (high temperature operating life test: +110°C, 500 hours), drift from temperature cycling (JESD22, Method A104-C, Method N, 500 cycles,

−40°C to +85°C), rate random walk (10 year projection), and broadband noise

2

Bias repeatability describes a long-term behavior over a variety of conditions. Short-term repeatability is related to the in-run bias stability and noise density

specifications.

3

The digital I/O signals use a 3.3 V system.

4

Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.

5

6

These times do not include thermal settling and internal filter response times, which may affect overall accuracy.

7

The RST line must be in a low state for at least 10 μs to assure a proper reset initiation and recovery.

8

The device functions at clock rates below 0.7 kHz but at reduced performance levels.

9

Supply current transients can reach 600 mA during start-up and reset recovery.

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