CS5530 datasheet(235/241 Pages) NSC

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Electrical Specifications (Continued)

Figure 5-6. Display TFT/TV Outputs Delays

Table 5-15. Video Interface: Setup/Hold and Delay Times

Symbol

Parameter

Min

Typ

Max

Units

Comments

Setup/Hold Times

tDisplaySetup

Display setup to rising PCLK:

VSYNC, HSYNC, FP_DISP_ENA,

FP_VSYNC, FP_HSYNC, PIXEL[23:0]

3.0

All setup/hold

times are

derived as

shown in

Figure 5-2.

tDisplayHold

Display hold from rising PCLK:

VSYNC, HSYNC, FP_DISP_ENA,

FP_VSYNC, FP_HSYNC, PIXEL[23:0]

tVID_VALSetup

VID_VAL setup to rising VID_CLK

3.75

tVID_VALHold

VID_VAL hold from rising VID_CLK

tVID_DATASetup

VID_DATA setup to rising VID_CLK

3.75

Also applies to

PIXEL[23;16]

when in 16-bit

video mode.

tVID_DATAHold

VID_DATA hold from rising VID_CLK

Delay Times

FPOUTMinDelay,

FPOUTMaxDelay

TFT/TV output delays from FP_CLK:

FP_DATA[17:0], FP_HSYNC_OUT,

FP_VSYNC_OUT,

FP_DISP_ENA_OUT, FP_ENA_VDD,

FP_ENA_BKL, FP_CLK_EVEN

0.1

5.2

All flat panel

applications use

the falling edge

of FP_CLK to

latch their data.

VID_RDYMinDelayE,

VID_RDYMaxDelayE

VID_RDY delay from falling VID_CLK

(early mode)

10.5

The mode for

VID_RDY (early

or normal) is set

with "Video Con-

figuration Regis-

ter"

VID_RDYMinDelayN,

VID_RDYMaxDelayN

VID_RDY delay from rising VID_CLK

(normal mode)

39.5

FP_CLK

FPOUTMinDelay

FPOUTMaxDelay

TFT/TV Outputs

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