RTL8201BL datasheet(23/29 Pages) ETC

Part #	RTL8201BL

Description	REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL

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Manufacturer	ETC [List of Unclassifed Manufacturers]

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RTL8201BL

2002-03-29

Rev.1.2

23

8.2.2 MII Timing of Reception Cycle

Shown is an example of transfer of a packet from PHY to MAC in MII interface

Symbol

Description

Minimum

Typical

Maximum

Unit

100Mbps

14

20

26

ns

t1

RXCLK high pulse width

10Mbps

140

200

260

ns

100Mbps

14

20

26

ns

t2

RXCLK low pulse width

10Mbps

140

200

260

ns

100Mbps

40

ns

t3

RXCLK period

10Mbps

400

ns

100Mbps

10

ns

t4

RXER, RXDV, RXD[0:3] setup to

RXCLK rising edge

10Mbps

6

ns

100Mbps

10

ns

t5

RXER, RXDV, RXD[0:3] hold after

RXCLK rising edge

10Mbps

6

ns

100Mbps

130

ns

t6

Receive frame to CRS high

10Mbps

600

ns

100Mbps

240

ns

t7

End of receive frame to CRS low

10Mbps

600

ns

100Mbps

150

ns

t8

Receive frame to sampled edge of

RXDV

10Mbps

3200

ns

100Mbps

120

ns

t9

End of receive frame to sampled

edge of RXDV

10Mbps

800

ns

RXCLK

RXD[0:3]

RXDV

RXER

V

IH(min)

V

IL(max)

V

IH(min)

V

IL(max)

t

4

t

5

t

1

t

3

t

2

RXCLK

RXDV

RXD[0:3]

CRS

TPRX+-

t

6

t

7

t

8

t

9

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RTL8201BL Datasheet(PDF) 23 Page - List of Unclassifed Manufacturers

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