ST72561 datasheet(261/262 Pages) STMICROELECTRONICS

261 / 262 page

ST72561

261/262

16 REVISION HISTORY

Date

Revision

Main changes

03-May 04

1.9

Added TQFP 10x10 package

Removed internal RC

Updated Figure 11 on page 22

Added note on monotonous VDD ramp on “Low Voltage Detector (LVD)” on page 26

Added caution ART Ext clock not avalaible in HALT see Section 10.3 on page 64

Added note “Once the OCIE bit is set both output compare features may trigger...” and

“Once the ICIE bit is set both input capture features may trigger...” in 8-bit timer Section 10.5.

Changed clock from fcpu/8000 to fosc2/8000 in Section 10.5 on page 94

Changed description of CSR register to read only except bit 2 R/W Section 10.5 on page 94

Added note to SPI slave freq. and updated Master mode procedure in Section 10.6 on page

112

Changed description of NF bit in Section 10.7.10

Removed “Configurable timer resolution” under "Time triggered communication option" from

Section 10.9 on page 172

Added Clearing interrupts limitation and SCI wrong break duration to “IMPORTANT

NOTES” on page 259

Removed beCAN Time triggered mode feature from Section 10.9 on page 172

Renamed CMSR RX and TX bits to REC and TRAN in Section 10.9 on page 172

Added beCAN FIFO corruption limitation Section 10.9.7.1 on page 189

Modified IINJ for Port B3 in Section 12.9.1 on page 236

11-May 04

2.0

Modified Clearing interrupts limitation in “IMPORTANT NOTES” on page 259

ST72561 Datasheet(PDF) 261 Page - STMicroelectronics