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LM12454CIV Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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LM12454CIV Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 43 page Converter Characteristics (Notes 6, 7, 8, 9, 19) (Continued) The following specifications apply to the LM12454, LM12458, and LM12H458 for V A+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12-bit + sign conversion mode, f CLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T A = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limits Unit (Note 10) (Note 11) (Limit) 8-Bit + Sign and “Watchdog” Mode ±1/8 LSB DC Common Mode Error Multiplexer Channel-to-Channel ±0.05 LSB Matching V IN+ Non-Inverting Input Range GND V (min) V A+ V (max) V IN− Inverting Input Range GND V (min) V A+ V (max) V IN+ −VIN− Differential Input Voltage Range −V A + V (min) V A+ V (max) Common Mode Input Voltage Range GND V (min) V A+ V (max) PSS Power Supply Zero Error V A+ = VD+ = 5V ±10% ±0.2 ±1.75 LSB (max) Sensitivity Full-Scale Error V REF+ = 4.5V, VREF− = GND ±0.4 ±2 LSB (max) (Note 15) Linearity Error ±0.2 LSB C REF V REF+/VREF− Input Capacitance 85 pF C IN Selected Multiplexer Channel Input 75 pF Capacitance Converter AC Characteristics (Notes 6, 7, 8, 9, 19) The following specifications apply to the LM12454, LM12458, and LM12H458 for V A+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12-bit + sign conversion mode, f CLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T A = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Parameter Conditions Typical Limits Unit (Note 10) (Note 11) (Limit) Clock Duty Cycle 50 % 40 % (min) 60 % (max) t C Conversion Time 13-Bit Resolution, 44 (t CLK) 44 (t CLK)+50ns (max) Sequencer State S5 ( Figure 15) 9-Bit Resolution, 21 (t CLK) 21 (t CLK)+50ns (max) Sequencer State S5 ( Figure 15) t A Acquisition Time Sequencer State S7 ( Figure 15)9 (t CLK) 9(t CLK)+50ns (max) Built-in minimum for 13-Bits Built-in minimum for 9-Bits and 2 (t CLK) 2(t CLK)+50ns (max) “Watchdog” mode t Z Auto-Zero Time Sequencer State S2 ( Figure 15)76 (t CLK) 76 (t CLK)+50ns (max) t CAL Full Calibration Time Sequencer State S2 ( Figure 15) 4944 (t CLK) 4944 (t CLK)+50ns (max) Throughput Rate 89 88 kHz (Note 18) LM12H458 142 140 (min) t WD “Watchdog” Mode Comparison Sequencer States S6, S4, 11 (t CLK) 11 (t CLK)+50ns (max) Time and S5 ( Figure 15) www.national.com 5 |
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