![]() |
Electronic Components Datasheet Search |
|
LM12L458 Datasheet(PDF) 23 Page - National Semiconductor (TI) |
|
|
|
LM12L458 Datasheet(HTML) 23 Page - National Semiconductor (TI) |
23 / 36 page ![]() 2.0 Internal User-Programmable Registers (Continued) 29 will go high at the start of a conversion or “watchdog” comparison and remain high until either have finished. See Instruction RAM “00”, Bit 8. Bits 8 and 9 form the RAM Pointer that is used to select each of a 48-bit instruction’s three 16-bit sections during read or write actions. A “00” selects Instruction RAM section one, “01” selects section two, and “10” selects section three. Bit 10 activates the Test mode that is used only during pro- duction testing. Leave this bit reset to “0”. Bit 11 is the Diagnostic bit and is available only in the LM12L458. It can be activated by setting it to a “1” (the Test bit must be reset to a “0”). The Diagnostic mode, along with a correctly chosen instruction, allows verification that the LM12L458’s ADC is performing correctly. When activated, the inverting and non-inverting inputs are connected as shown in Table 1. As an example, an instruction with “001” for both V IN+ and VIN− while using the Diagnostic mode typi- cally results in a full-scale output. 2.3 INTERRUPTS The LM12L458 has eight possible interrupts, all with the same priority. Any of these interrupts will cause a hardware interrupt to appear on the INT pin (31) if they are not masked (by the Interrupt Enable register). The Interrupt Status regis- ter is then read to determine which of the eight interrupts has been issued. TABLE 1. LM12L458 Input Multiplexer Channel Configuration Showing Normal Mode and Diagnostic Mode Channel Selection Data Normal Diagnostic Mode Mode V IN+ V IN− V IN+ V IN− 000 IN0 GND 001 IN1 IN1 V REF+ V REF− 010 IN2 IN2 IN2 IN2 011 IN3 IN3 IN3 IN3 100 IN4 IN4 IN4 IN4 101 IN5 IN5 IN5 IN5 110 IN6 IN6 IN6 IN6 111 IN7 IN7 IN7 IN7 The Interrupt Status register, 1010 (A4–A1, BW = 0) or 1010x (A4–A0, BW = 1) must be cleared by reading it after writing to the Interrupt Enable register. This removes any spurious interrupts on the INT pin generated during an Inter- rupt Enable register access. Interrupt 0 is generated whenever the analog input voltage on a selected multiplexer channel crosses a limit while the LM12L458 are operating in the “watchdog” comparison mode. Two sequential comparisons are made when the LM12L458 are executing a “watchdog” instruction. Depend- ing on the logic state of Bit 9 in the Instruction RAM’s second and third sections, an interrupt will be generated either when the input signal’s magnitude is greater than or less than the programmable limits. (See the Instruction RAM, Bit 9 de- scription.) The Limit Status register will indicate which pre- programmed limit, #1or #2 and which instruction was ex- ecuting when the limit was crossed. Interrupt 1 is generated when the Sequencer reaches the instruction counter value specified in the Interrupt Enable register’s bits 8–10. This flag appears before the instruc- tion’s execution. Interrupt 2 is activated when the Conversion FIFO holds a number of conversions equal to the programmable value stored in the Interrupt Enable register’s Bits 11–15. This value ranges from 0001 to 1111, representing 1 to 31 conver- sions stored in the FIFO. A user-programmed value of 0000 has no meaning. See Section 3.0 for more FIFO information. The completion of the short, single-sampled auto-zero cali- bration generates Interrupt 3. The completion of a full auto-zero and linearity self-calibration generates Interrupt 4. Interrupt 5 is generated when the Sequencer encounters an instruction that has its Pause bit (Bit 1 in Instruction RAM “00”) set to “1”. Interrupt 7 is issued after a short delay (10 ms typ) while the LM12L458 returns from Standby mode to active operation using the Configuration register’s Bit 4. This short delay al- lows the internal analog circuitry to settle sufficiently, ensur- ing accurate conversion results. 2.4 INTERRUPT ENABLE REGISTER The Interrupt Enable register at address location 1001 (A4–A1, BW = 0) or 1001x (A4–A0, BW = 1) has READ/ WRITE capability. An individual interrupt’s ability to produce an external interrupt at pin 31 (INT) is accomplished by plac- ing a “1” in the appropriate bit location. Any of the internal interrupt-producing operations will set their corresponding bits to “1” in the Interrupt Status register regardless of the state of the associated bit in the Interrupt Enable register. See Section 2.3 for more information about each of the eight internal interrupts. Bit 0 enables an external interrupt when an internal “watch- dog” comparison limit interrupt has taken place. Bit 1 enables an external interrupt when the Sequencer has reached the address stored in Bits 8–10 of the Interrupt En- able register. Bit 2 enables an external interrupt when the Conversion FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable reg- ister, has been reached. Bit 3 enables an external interrupt when the single-sampled auto-zero calibration has been completed. Bit 4 enables an external interrupt when a full auto-zero and linearity self-calibration has been completed. Bit 5 enables an external interrupt when an internal Pause interrupt has been generated. Bit 6 is a “Don’t Care”. Bit 7 enables an external interrupt when the LM12L458 re- turn from power-down to active mode. Bits 8–10 form the storage location of the user-programmable value against which the Sequencer’s address is compared. When the Sequencer reaches an ad- dress that is equal to the value stored in Bits 8–10, an inter- nal interrupt is generated and appears in Bit 1 of the Interrupt Status register. If Bit 1 of the Interrupt Enable register is set to “1”, an external interrupt will appear at pin 31 (INT). The value stored in bits 8–10 ranges from 000 to 111, repre- senting 0 to 7 instructions stored in the Instruction RAM. Af- ter the Instruction RAM has been programmed and the RE- SET bit is set to “1”, the Sequencer is started by placing a “1” in the Configuration register’s START bit. Setting the INT 1 trigger value to 000 does not generate an INT 1 the first www.national.com 23 |
Similar Part No. - LM12L458 |
|
Similar Description - LM12L458 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |