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STM32F427XX Datasheet(PDF) 31 Page - STMicroelectronics |
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STM32F427XX Datasheet(HTML) 31 Page - STMicroelectronics |
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31 / 239 page  DocID024030 Rev 9 31/238 STM32F427xx STM32F429xx Functional overview 43 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability 3.19 Real-time clock (RTC), backup SRAM and backup registers The backup domain includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary- coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 3.20: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.20: Low-power modes). Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP100 Yes No Yes No LQFP144, LQFP208 Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor WLCSP143, LQFP176, UFBGA169, UFBGA176, TFBGA216 Yes BYPASS_REG set to VSS Yes BYPASS_REG set to VDD |
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