FOR AUTOMOTIVE 125°C OPERATION 2-WIRE CONVENIENCE TIMER

S-35710 Series

25



RST

________

Pin

1. Chattering elimination

The RST

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pin has a built-in chattering elimination circuit, and the output logic is active "L".

Figure 34 is a timing chart of chattering elimination. Perform sampling at 8 Hz and operate the shift register circuit.

Perform the shift operation for 3 times, and reset the counter when DF1 to DF3 are all "L". During the charttering

elimination, the pulse width, 2 periods (approximately 0.25 seconds) of clock (8 Hz), can be eliminated. To determine

the RST

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pin "L" input, maintain the RST

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pin "L" input during the period longer than 3.5 periods (0.438 seconds) of

clock (8 Hz). Similarly, to determine the RST

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pin "H" input, maintain the RST

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pin "H" input during the period longer

than 3.5 periods (0.438 seconds) of clock (8 Hz).

Clock (8 Hz)

RST

________

pin input signal

Shift register_DF1

Shift register _DF2

Shift register _DF3

Reset signal after

chattering elimination

2 periods

3.5 periods

3.5 periods

Chattering elimination width

Count-up action starts

Counter reset

Figure 34 Timing Chart of Chattering Elimination

2. Operation at power-on

At power-on, the reset signal after chattering elimination is "L" regardless of the RST

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pin status. Consequently, the

S-35710 Series becomes initial status (Refer to "Figure 16 Status Transition Diagram of One-shot Loop

Time-out (Nch Open-drain Output)", "Figure 17 Status Transition Diagram of One-shot Loop Time-out (CMOS

Output)" and "Figure 20 Status Transition Diagram of Handshake Time-out (Nch Open-drain Output)",

"Figure 21 Status Transition Diagram of Handshake Time-out (CMOS Output)") and can not perform write

operation to the wake-up time register. When the reset signal after chattering elimination is "L", the no acknowledge is

output in the 2nd or subserquent bytes if write operation is performed to the wake-up time register.

If the crystal oscillation circuit starts to oscillate after power-on, the clock operates and the reset signal after chattering

elimination becomes "H", the S-35710 Series then migrates to read mode. This makes the write operation to the

wake-up time register possible. Figure 35 shows the timing chart at power-on.

The write-disable time period of the wake-up time register showed in Figure 35 changes according to the oscillation

start time. If the no acknowledge is output from the S-35710 Series at the time of write operation to the wake-up time

register immediately after power-on, it is recommended to set a time interval of approximately 0.5 seconds to 1 second

for the next communication until the oscillation is stabilized.

Clock (8 Hz)

Write-disable time period of wake-up time register

RST

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pin input signal

Shift register_DF1

Shift register_DF2

Shift register_DF3

Reset signal after

chattering elimination

VDD

Migrate to read mode

Figure 35 Timing Chart at Power-on