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C8051F54X Datasheet(PDF) 48 Page - Silicon Laboratories |
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C8051F54X Datasheet(HTML) 48 Page - Silicon Laboratories |
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48 / 276 page  C8051F54x 48 Rev. 1.1 6.2. Electrical Characteristics Table 6.2. Global Electrical Characteristics –40 to +125 °C, 24 MHz system clock unless otherwise specified. Parameter Conditions Min Typ Max Units Supply Input Voltage (VREGIN) 1.8 — 5.25 V Digital Supply Voltage (VDD) System Clock < 25 MHz System Clock > 25 MHz VRST 1 —2.75 V 2 — 2.75 Analog Supply Voltage (VDDA) (Must be connected to VDD) System Clock < 25 MHz System Clock > 25 MHz VRST 1 —2.75 V 22.75 Port I/O Supply Voltage (VIO) Normal Operation 1.82 —5.25 V Digital Supply RAM Data Retention Voltage —1.5 — V SYSCLK (System Clock)3 0— 50 MHz TSYSH (SYSCLK High Time) 9 — — ns TSYSL (SYSCLK Low Time) 9 — — ns Specified Operating Temperature Range –40 — +125 °C Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) IDD 4 VDD = 2.1 V, F = 200 kHz — 85 — µA VDD = 2.1 V, F = 1.5 MHz — 600 — µA VDD = 2.1 V, F = 25 MHz — 9.2 11 mA VDD = 2.1 V, F = 50 MHz — 17 21 mA IDD 4 VDD = 2.6 V, F = 200 kHz — 120 — µA VDD = 2.6 V, F = 1.5 MHz — 920 — µA VDD = 2.6 V, F = 25 MHz — 13 21 mA VDD = 2.6 V, F = 50 MHz — 22 33 mA IDD Supply Sensitivity 4 F = 25 MHz — 68 — %/V F = 1 MHz — 77 — %/V IDD Frequency Sensitivity 4,5 VDD = 2.1 V, F < 12.5 MHz, T = 25 °C — 0.43 — mA/MHz VDD = 2.1 V, F > 12.5 MHz, T = 25 °C — 0.33 — mA/MHz VDD = 2.6 V, F < 12.5 MHz, T = 25 °C — 0.60 — mA/MHz VDD = 2.6 V, F > 12.5 MHz, T = 25 °C — 0.42 — mA/MHz Notes: 1. Given in Table 6.4 on page 52. 2. VIO should not be lower than the VDD voltage. 3. SYSCLK must be at least 32 kHz to enable debugging. 4. Guaranteed by characterization. Does not include oscillator supply current. 5. IDD estimation for different frequencies. 6. Idle IDD estimation for different frequencies. |
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